The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a method of providing resistors embedded in aspect ratio trapping structures (ART).
One way of improving the performance of CMOS devices is to utilize high mobility semiconductor channel materials. For example, III-V compound semiconductor materials have been touted for future technology nodes owning to their high carrier mobility. Unfortunately, dislocation defects typically arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material—often referred to as “heterostructure”—due to different crystalline lattice sizes of the two materials. This lattice mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure.
Aspect ratio trapping (ART) is one way to overcome the lattice mismatch, however ART uses trenches or pillars with dielectric, i.e., oxide or nitride sidewalls, to grow the III-V epitaxy. Those dielectric regions consume area, which is contrary to the shrinking requirements of future smaller device nodes. Dielectric region not used for creating semiconductor device structures, such as transistors, are generally removed in the finished wafer.
Accordingly, what is needed, but has so far not been provided in the art, is to make use of unused ART structures formed using the ART process.